Phase locked loops are typically equipped with controlled oscillators, for example a voltage controlled oscillator (VCO). The VCO is coupled in a feedback loop in order to generate a high frequency clock from a low frequency reference clock. This reference clock is of a lower frequency since it is easier to generate various stable and precise clock signals at lower frequencies. An example of a phase locked loop according to the prior art is shown in FIG. 1. There is a VCO, a phase frequency detector PFD, a charge pump, a divider and a compensation capacitor C1SVS, an integrating analog element including a resistor R and a capacitor C2. The phase frequency detector PFD compares the phase of the reference clock REFCKL with the phase of the feedback clock signal SYSCLK which have basically the same clock frequency. The feedback clock signal SYSCLK is the clock signal PLLOUT output by the PLL and divided by the divider DIV. If the frequency or the phase of the feedback clock signal SYSCLK differs from the phase or frequency of the reference clock signal REFCLK, the charge pump CP applies a signal to the VCO in order to increase or decrease the phase or frequency of the output signal PLLOUT of the VCO. The signal ICH issued by the charge pump is a function of the difference between the reference clock REFCLK and the feedback clock signal SYSCLK.
The VCO may be implemented as a ring oscillator. The ring oscillator topology provides a series of cascaded delay stages (typically inverters). The output signal from the last delay stage is fed back to the input of the first delay stage. The total delay through the cascaded stages (including any net inversion of the signal within the system) is designed to satisfy criteria for sustained oscillation. Typically each delay stage has a variable delay governed by an independent input. The oscillation frequency of the VCO is then controlled by the input signal in order to vary the stage delay. The oscillation frequency for a ring oscillator can be tuned over a wide range, as for example 20% to 50% of the nominal center frequency of the VCO.
Prior art PLLs employ real time clock input signals in the range of 32 KHz and generate output signals PLLOUT with frequencies in the range of tens to hundreds of MHz. In order to comply with this rather low input frequency, the PLL has to have a very small bandwidth, for example in the range of 1 to 3 KHz or even smaller. Such a small bandwidth requires external components and also consumes a lot of power, in particular in case of digital PLLs. However, handheld and mobile devices require reducing the power consumption and the number of external components.